Lecture 1 - Introduction to FPGA
Lecture 2 - Technology Review - Part 1
Lecture 3 - Technology Review - Part 2
Lecture 4 - DSP and Integrated Design Suites
Lecture 5 - Introduction to Verilog
Lecture 6 - Verilog
Lecture 7 - Modelling of Digital Circuits
Lecture 8 - Modelling of Digital Circuits and Testbench - Part 1
Lecture 9 - Modelling of Digital Circuits and Testbench - Part 2
Lecture 10 - Testbench, Simulation, and Synthesis
Lecture 11 - Structural Modelling of Combinational Logic
Lecture 12 - Dataflow Modelling of Combinational Logic
Lecture 13 - Behavioral Modelling of Combinational Logic
Lecture 14 - Simulation of Combinational Logic Circuits - Part 1
Lecture 15 - Simulation of Combinational Logic Circuits - Part 2
Lecture 16 - Sequential Logic Circuits - Part 1
Lecture 17 - Sequential Logic Circuits - Part 2
Lecture 18 - Blocking and Non-Blocking Statements
Lecture 19 - Sequential Logic Circuits: Blocking and Non-Blocking Statements, Counters
Lecture 20 - Counters and Shift Registers
Lecture 21 - Finite State Machines - Part 1
Lecture 22 - Finite State Machines - Part 2
Lecture 23 - Finite State Machines: Sequence Detector
Lecture 24 - FSM: Verilog Modules of Sequence Detector
Lecture 25 - FSM: Counters
Lecture 26 - Memory Banks
Lecture 27 - FSM Modelling Styles
Lecture 28 - FSM Modelling Styles and Timing Control
Lecture 29 - Timing Controls - Part 1
Lecture 30 - Timing Controls - Part 2
Lecture 31 - Synthesis of Combinational Logic Circuits
Lecture 32 - Synthesis of Sequential Logic Circuits - Part 1
Lecture 33 - Synthesis of Sequential Logic Circuits - Part 2
Lecture 34 - Synthesis of Sequential Logic Circuits - Part 3
Lecture 35 - Synthesis of Finite State Machines
Lecture 36 - Arithmetic Basics - Part 1
Lecture 37 - Arithmetic Basics - Part 2
Lecture 38 - Arithmetic Basics - Part 3
Lecture 39 - CORDIC
Lecture 40 - Timing Analysis
Lecture 41 - Finite Impulse Response Filters - Part 1
Lecture 42 - Finite Impulse Response Filters - Part 2
Lecture 43 - Finite Impulse Response Filters - Part 3
Lecture 44 - Finite Impulse Response Filters - Part 4
Lecture 45 - Digital FIR Filters - Verilog Codes
Lecture 46 - Infinite Impulse Response Filters - Part 1
Lecture 47 - Infinite Impulse Response Filters - Part 2
Lecture 48 - Infinite Impulse Response Filters - Part 3
Lecture 49 - Digital IIR Filters: Verilog Codes - Part 1
Lecture 50 - Digital IIR Filters: Verilog Codes - Part 2
Lecture 51 - DFT
Lecture 52 - Sliding DFT and its Variants - Part 1
Lecture 53 - Sliding DFT and its Variants - Part 2
Lecture 54 - DCT
Lecture 55 - FFT and DSP Builder Models
Lecture 56 - General Discrete-Signal Processing Network - Part 1
Lecture 57 - General Discrete-Signal Processing Network - Part 2
Lecture 58 - Adaptive Filtering - Part 1
Lecture 59 - Adaptive Filtering - Part 2
Lecture 60 - Adaptive Filtering - Part 3
Lecture 61 - Combinational Logic Circuits: Simulation
Lecture 62 - Sequential Logic Circuits: Simulation
Lecture 63 - Finite State Machines: Simulation
Lecture 64 - Timing Controls: Simulation
Lecture 65 - Lab 1 : Part 2 : Combinational Logic Circuits: Implementation
Lecture 66 - Lab 2 : Part 2 : Sequential Logic Circuits: Implementation
Lecture 67 - Lab 3 : Part 2 : Finite State Machines: Implementation
